1. FIELD OF THE INVENTION
This invention relates to a display data synthesizer circuit, or more in particular to an improvement in the display data synthesizer circuit used for a display panel which displays a desired pattern by selective excitation of a multiplicity of display elements included in the display panel.
2. DESCRIPTION OF THE PRIOR ART
A well-known display panel has a multiplicity of display elements and displays a desired pattern such as characters and symbols by selective excitation of the display elements. An example is a display panel of liquid crystal matrix type. In this type of display panel, the display elements are generally divided into a plurality of sections. For selective excitation of the display elements, the plurality of sections are driven sequentially in accordance with a predetermined order. In driving each section, selected display elements of that particular section are simultaneously excited for a predetermined period of time. In order to control the selective excitation of the display elements in driving each section according to the desired display pattern, a display data synthesizer circuit synthesizes the display data corresponding to each section. It maintains the particular display data and applies it to a drive circuit during a predetermined driving period for that section. In order to obtain a clear display pattern, it is necessary that there is no substantial interval between the driving periods for successive sections. In order to achieve this object, a conventional display data synthesizer circuit includes a parallel output shift register and a latch circuit. The parallel output shift register stores the bits of a display data for one section applied thereto in bit-series and produces them in parallel. The latch circuit receives the bits of the display data in parallel from the shift register, holds it for a predetermined period of time, and during that period, applies the display data to the drive circuit in parallel. As long as the latch circuit applies to the drive circuit the display data held thereby, the parallel output shift register receives and stores the display data for the next section. In view of the fact that each section generally contains a great number of display elements and that the display data for each section includes bits in the number equal to that of the display elements, the latch circuit, which receives in parallel signals corresponding to the bits of the display data for each section and produces the same signals in parallel, requires terminals in the number at least twice that of the bits. Therefore, in the case where a display data synthesizer circuit is assembled in IC packages with, say, 14, 16 or 32 terminal pins, a great number of the IC packages are required, thus posing the problems of consumption of long time for wiring work.